Warranty will be lost.
DST-00 can be configured with 6 power inputs.
SYS-CORE(5V DC connector 5.5/2.1
SYS-IO (3.3V generate from SYS-CORE
LVDS-IF (3.3V DC connector 5.5/2.5
FPGA-IO (3.3V connect from LVDS-IO
CLOCK44 (3.3V connect from FPGA-IO
CLOCK48 (3.3V connect from FPGA-IO
schematic net name
OrangePi-I2S-DevKit-R3
SYS-CORE -> 5V (typ 400mA
SYS-IO -> 3.3V (under 100mA
OrangePi LVDS-R4
LVDS-IF -> IF3.3V (typ 250mA
FPGA-IO -> 3.3V (under 50mA
CLOCK44 -> 3.3V44 (under 50mA
CLOCK48 -> 3.3V48 (under 50mA
CLOCK44 separate
Remove for L3 Filter
Supply 3.3V to P3 Connector
CLOCK48 separate
Remove for L4 Filter
Supply 3.3V to P4 Connector
LVDS-IF and FPGA-IF separate
Remove for L1 Filter
Remove for DC connector
Supply 3.3V to P1 Connector ( LVDS-IF
Supply 3.3V to P2 Connector ( FPGA-IF
SYS-IO and SYS-CORE separate
pull up IOV-DISABLE (short jumper IOV-DISABLE to R4 (stop generate 3.3V on OrangePI
Supply 5V-5.2V to P1 Connector ( SYS-CORE
Supply 3.3V to P2 Connector ( SYS-IO
