| Pin | Name | Function |
| 1 | Diff1_P | I2S Data Output Differential Positive |
| 2 | Diff1_Shilde | Shilde 1/GND |
| 3 | Diff1_N | I2S Data Output Differential Negative |
| 4 | Diff2_P | I2S Clock Output Differential Positive |
| 5 | Diff2_Shilde | Shilde 2/GND |
| 6 | Diff2_N | I2S Clock Output Differential Negative |
| 7 | Diff3_P | I2S SYNC Output Input Differential Positive |
| 8 | Diff3_Shilde | Shilde 3/GND |
| 9 | Diff3_N | I2S SYNC Output Differential Negative |
| 10 | Diff4_P | Master Clock Output Differential Positive |
| 11 | Diff4_Shilde | Shilde 4/GND |
| 12 | Diff4_N | Master Clock Output Differential Negative |
| 13 | 48 | 48KHz or 44.1KHz / Control Output 1 |
| 14 | ClkIn_P | Master Clock Input Differential Positive / Control Output 2 |
| 15 | PCM | PCM or DSD / SCL / Control Output 3 |
| 16 | Mute | Mute or Play / SDA / Control Output 4 |
| 17 | GND | Shilde 5 / GND / Control Output 5 |
| 18 | Detect | Detect Connection / Control Output 6 (5V tolerance) |
| 19 | ClkIn_N | Master Clock Input Differential Negative / Control Output 7 |
Resiver Register
| Pin | Passive | Active |
| 13 | open | week pull-down Low=44.1KHz High=48kHz |
| 15 | pull-down Low=PCM High=DSD | connet 10k to 13pin invert (Low=DSD High=PCM / I2C SCL |
| 16 | pull-down Low=Mute High=Play | pull-up 10k invert (Low=Play High=Mute / I2C SDA |
| 18 | open | week pull-down Low=I2C mode High=Connect |
Passive
Active
Transmitter Differential Signal
| Name | Direction | Function |
| Diff1 | Output | I2S Data / DSD Right |
| Diff2 | Output | I2S Clock / DSD Clock |
| Diff3 | Output | I2S SYNC / DSD LKeft |
| Diff4 | Output | Master Clock Output |
| ClkIn | Input | Master Clock Input |
ActiveMode
do not use ClkIn
Mute is Invert
PassiveMode